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[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 1 - general description the AK4688 is a stereo audio codec . the integrated adc and dac inte rfaces accept u p to 24-bit input/output data and sup port an asyn ch ronous op eration. the input rang e o f the pre-amplifier, that supports line inputs, is adj ustable by a n extern al re sistor. a gr ound refe renc ed 2vrms output with a 3.3v single power supply is achieve d by an integrat ed charge p u mp, reducing ext e rnal pa rts such as ac-coupling capacitors a nd mute ci rcuits. the adc block of the ak 4688 achieves a dyn a mic range of 99db, and the dac block achieves a dynamic rang e of 105db. the AK4688 is suitable for digital recording systems , digital tvs , blu-ray recorders and h o me theater sy stems . features ? asy n chro nous adc/dac operatio n ? capless stereo pre- amplifier for line input/output ? 24bit stereo adc - 64x over s a mpling - sampling rate up to 48khz - linear phase digital anti-alias filt er - s/(n+d): 8 3 db - d y n a mic range, s/n: 99db - digital hpf for offset cancellatio n ? 24bit stereo dac - 128x ove r sampling - sampling rate up to 192khz - 24bit 8 times digital filter - s/(n+d): 9 5 db - d y n a mic range, s/n: 105db - de-empha sis filter ? high jitter tolerance ? external master clock input: 256fs, 38 4fs , 512fs 768 f s (fs=3 2khz 48khz) 128fs, 19 2fs , 256fs 384 f s (fs=6 4khz 96khz) 128fs, 19 2fs (fs=12 8khz ~ 192khz) ? 2 audio s e rial i/f (port1, port2) - master/slave mode (port1) - i/f format port1, 2: msb, lsb justified (16/24 bit), i 2 s ? hard w a re / i 2 c-bus control ? operating voltage: - digital i/o and charge pump: 3.0v 3.6v - adc analo g : 3.0v 3.6v - dac analo g : 3.0v 3.6v ? package: 36pin qfn AK4688 asynchronous stereo codec with capless line i/o http://
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 2 - 2ch a dc c vee cp cn lo u t ro u t m c lk 1 bi c k1 l rck 1 sd t o ms n port1 2v r ms hpf ser i a l i/ f 2v r ms +/-50mv d c i n put pwad bit pdn1 pin mclk2 bick2 lrck2 sdti port2 2ch da c se ria l i/f sda scl control i/f a vdd1 a vss1 a vdd2 a vss2 dvdd dvss vref charge pump de -e m lin rin i2c pdn2 pdn1 lo li ri ro cad0/cks pwad/pwda bit pdn1/pdn2 pin pwda bit pdn2 pin fi gu re 1. a k 4 68 8 b l ock di a g ram
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 3 - ordering guide a k46 88 en - 2 0 a +8 5 q c 36 pi n q f n ( 0. 5m m pi t c h) a kd4 688 ev alu a tion b oar d fo r th e ak4 688 pin lay o ut 36 pi n qf n (0 . 5m m pi t c h) lo li rin nc lin i2 c msn sd a ro r1 a vdd1 a vss1 a vss2 a vdd2 rout sdto lrck1 bick1 mclk1 pdn1 pdn2 mclk2 bick2 cn cp d vss dv dd tes t 2 tes t 1 ca d0 stdi a k4688 top view 28 29 30 31 32 33 34 35 27 26 25 17 16 15 14 13 12 11 10 24 23 22 21 20 1 2 3 4 5 6 7 8 36 19 cvee 18 lrck2 9 vref lout sc l
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 4 - pin/function no . pi n nam e i/ o fu nct i on 1 sdt o o audio serial data output pin (for port1) 2 lr c k1 i/ o channel clock pin (for port1) 3 b ic k 1 i/ o audio serial data clock pin (for port1) 4 m c lk1 i adc master clock input pin (for port1) 5 pdn1 i pow e r- dow n mo d e fo r ad c whe n ? l?, t h e adc is powered-down. 6 pdn2 i pow e r- dow n mo d e fo r da c whe n ? l?, t h e dac is powered-down. 7 m c lk2 i dac master clock input pin (for port2) 8 b ic k 2 i audio serial data clock pin (for port2) 9 lr c k2 i input channel clock pin (for port2) 1 0 sd ti i audio serial data input pin (for port2) c ad 0 i cad address pin (i2c pin = ?h?) 11 cks i adc m c lk s p eed sel ect pi n (i 2c pi n = ? l ?) ?h?: mclk= 7 68fs, ?l?: mc lk= 2 56fs 12 test 1 i thi s pi n m u st be c o n n ect ed t o t h e g r ou n d 13 test 2 i thi s pi n m u st be c o n n ect ed t o t h e g r ou n d 14 dv d d - digital power supply pin, 3.0v 3.6v 1 5 d v ss - digital ground pin, 0v 1 6 cp i positive charge pump capacitor terminal pin (for analog input/output) 17 c n i negative charge pump capacitor terminal pin (for analog input/output) 18 c v ee o charge pump circuit negative voltage output pin (for analog input/output) 19 r out o rch analog output pin 20 lo ut o lch analog output pin 21 vref o r e fere nce out put pi n connect to avss2 with a 1f low esr capacitor over all temperatures. 22 av d d2 - dac analog power supply pin, 3.3v 3.6v 2 3 a v ss2 - adc analog ground pin, 0v 2 4 a v ss1 - adc analog ground pin, 0v 25 av d d1 - adc analog power supply pin, 3.0v 3.6v 26 r i o rch feedback resistor input pin 27 r o o rch feedback resistor output pin 28 lo o lch feedback resistor output pin 29 li o lch feedback resistor input pin 30 r in i rch input pin 31 nc - this pin must be connected to the ground 32 lin i lch input pin 33 i2c i i 2 c pin ?h?= i 2 c control, ?l?= h/w control 34 sd a i/o c ont r o l dat a p i n (i 2c pi n = ?h?) when the i2c pin = ?l? (h/w control), the sda pin must be connected to dvss. 35 sc l i c ont r o l dat a c l ock pi n ( i2c pi n = ?h? ) when the i2c pin = ?l? (h/w control), the scl pin must be connected to dvss. 36 m s n i por t 1 m a st er m o de sel ect p i n. ?l?(connected to the gr oun d) : slav e m o d e . ?h? ( connected to dvdd) : master m ode. note: all digital input pins must not be allowed to float.
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 5 - absolute maximum ratings (avs s1= a vs s2= d vss= 0v; note 1 ) par a meter sym bol min max unit po wer s u p p ly dv d d a vdd 1 avdd2 -0 .3 -0 .3 -0 .3 4. 0 4. 0 4. 0 v v v in p u t cu rre nt ( a ny pi ns e x ce p t fo r s u pplies) ii n - 10 ma dig ital in pu t vo ltag e (mclk1 -2 , pdn1-2, lrck1 - 2 , sdti, bick1-2, sda, scl, msn, cad0 pins ) v i nd - 0. 3 d vdd +0. 3 v anal og i n put vol t a ge (lin1-3, rin1-3 pins) vi n a -0 .3 av d d1+ 0. 3 v am bi ent ope r at i ng tem p erat ure ta -2 0 85 c st ora g e tem p erat ure tst g -6 5 15 0 c not e 1. a v s s 1 , a v ss 2 a n d dv ss m u st be co nnect e d t o t h e sam e anal o g gr o u n d pl ane . war n ing: op eration at o r beyo nd th ese limits m a y resu l t in p e rm an en t d am ag e to th e d ev i ce. norm al operation is not gua r antee d at thes e extrem es. recommended operating co nditions (avs s1= a vs s2= d vss= 0v; note 1 ) parameter symbol min typ max unit power s u pply ( note 2 ) d vdd a vdd 1 a vdd 2 3. 0 3. 0 3. 0 3. 3 3. 3 3. 3 3. 6 3. 6 3. 6 v v v n o te 2 . th e av dd1 an d avd d2 m u st b e th e sam e v o ltage. the v o l t a ge di f f ere n ce bet w ee n dv d d a n d o t her v o l t a ges ( a v d d 1 an d a v d d 2 ) m u st be l e ss t h a n 0. 3 v . * a km assu m e s no resp on sib i lity fo r th e usag e b e yon d th e co nd itio ns in th is d a tash eet.
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 6 - analog c hara cter istics (ta=2 5 c; avd d1 =a vdd 2 = dvd d = 3. 3v ; av ss1 = av ss2 = d vss =0 v ; f s =4 8khz; bi ck =6 4f s; sig n a l fr equ e ncy=1 k h z ; 24b it d a ta; measure m en t fr eq u e ncy = 20 h z 2 0 k hz at fs= 4 8k hz, 2 0 hz~ 4 0k hz at fs=9 6 k h z ; 20 hz~ 4 0 k h z a t fs=1 9 2 k h z, a l l bl ock s are sy nch r oni ze d, u n l ess ot he r w i s e speci fi ed ) parameter min typ max unit pre-amp characteristics: feedback resistance rf 12 39 92 k input resistance ri 18 47 92 k out put level lo / ro pins ( a dc=0dbfs ) ( no te 3 ) 1. 82 1. 91 2. 00 vrm s loa d resistanc e r l ( no te 4 ) 18 k loa d capacita nce c l ( no te 4 ) 20 pf analog input (lin, rin pin) to adc analog input characteristics reso lu tion 2 4 bits s/(n+ d ) (- 1 d bfs ) fs=4 8 k hz - 83 db dr (- 60db fs) fs=4 8 k hz , a- wei g ht ed - 99 db s/ n (i np ut of f) fs=4 8 k hz , a- wei g ht ed - 99 db interc ha nnel is olation ( note 5 ) - 10 0 db int e rc ha nnel g a i n m i sm at ch 0 - db gain drift 5 0 - ppm / c power s u pply rejection ( note 6 ) 50 db dac to analog output (lout, rout pin) characteristics reso lu tion 2 4 bits s/(n+ d ) ( 0 dbfs ) fs=4 8 k hz f s =96k h z f s =192 kh z - - - 95 93 93 db db db dr (- 60db fs) fs=48khz , a- weighted fs=9 6 k hz , a- weig hted f s =192 kh z, a-w e igh ted - - - 105 105 105 db db db s/n (? 0? data) fs=48khz , a- weighted fs=9 6 k hz , a- weig hted f s =192 kh z, a-w e igh ted - - - 105 105 105 db db db interchannel isol at i on - 10 0 db in terch a n n el gain mism a t ch 0 - db dc of fset (at output pi n ) ?5 0 +5 m v gain drift 50 - ppm/ c out put voltag e lo ut/ r o ut = 2 x a vd d 2 / 3 . 3 1. 85 2 2. 15 vrm s loa d resistanc e 5 k load capacita nce (c 1) 30 pf power s u pply rejection ( note 6 ) 62 db no te 3. in pu t ran g e for adc fu ll scale wh en th e ex tern al inp u t resistan ce i s 4 7 k , fee d ba ck resistance is 39k and in pu t si gnal i s 2. 3 v r m s. note 4. r l or c l of figure 3. loa d resistanc e and ca pacitance whe n t h e ou tpu t sign al o f th e lo/ro p in is u s ed fo r an external de vice . no te 5 . th is valu e is th e ch an n e l iso latio n fo r all o th e r ch an n e ls b e t w een lin and r i n. n o te 6 . psr is ap p lied to avd d1 , avd d2 an d dvd d w i th 1 kh z , 50 m v p p.
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 7 - 470 2 . 2nf analog out c1 lout/rout a k 46 88 fi gu re 2. li ne out c i rc ui t e x a m pl e adc li lo 0v r f r i 0v lin (r l ) (c l ) - + ak 4 6 8 8 fi gu re 3. ext e r n al c i rcui t of p r e - am p
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 8 - power s uppli es parameter min typ max unit pow e r su pp ly cu rr en t no rm al operat i on (p d n 1 pi n = pd n 2 pi n = ?h?) a vvd 1 a vdd 2 d vdd d vdd +avdd 1 + av dd2 po wer -d o wn m ode (p d n 1 pi n = p d n 2 pi n = ? l ?; note 7 ) d vdd +avdd 1 + av dd2 3 11 13 27 1 - - - 40 20 ma ma ma ma a not e 7. p d n 1 - 2 a n d tes t1 - 2 pi ns are hel d at dv ss, an d al l di gi t a l i n p u t s i n cl u d i n g cl o c k pi ns (m c l k1 - 2 , b i c k 1- 2, lr c k 1 - 2 , s d ti, sd a, sc l, m s n a n d c a d0 pi ns) a r e he ld at dv dd o r d v ss. how e ver, th e lrck an d bick pi ns sh o u l d be ope n si nce t h es e pi n s becom e out put st at e w h en t h e m s n pi n i s fi xe d t o d v d d . filter characteris tics (ta=2 5 c; avd d1 =a vdd 2= dv dd = 3 . 3v ; f s =48 kh z ) parameter symbol min typ max unit adc digital filter (decimation lpf): passba n d ( note 8 ) 0.1d b -0 .2 db -3 .0 db pb 0 - - 21 .1 21 .7 18 .8 - - khz khz khz st op ba nd sb 28 .5 khz st op ba nd at t e nuat i o n sa 73 db gr oup delay ( no te 10 ) gd 17 1/ fs group delay distortion gd 0 s adc digital filter (hpf): fre que ncy r e s p o n se ( note 8 ) -3 db -0 .1 db fr 1. 0 7. 1 hz hz dac digital filter: passba n d 0. 0 5db ( no te 9 ) - 6 . 0 db pb 0 - 24 .0 21 .7 - khz khz st op ba nd ( n o t e 9 ) sb 26 .3 khz passba n d ripple pr 0. 05 db st op ba nd at t e nuat i o n sa 64 db group delay ( note 10) gd - 24 - 1/fs de-em p h asis filter (dem = on) de-em phasis e r ror (dc re fere nce ) f s = 32 kh z f s = 44 .1 kh z f s = 48 kh z - - - - - - ?1 .5/ 0 ?0 .2/ + 0. 2 0/ +0. 6 db db db dac digital filter + analog filter: (dem = off) fre que ncy r e s p o n se 2 0 .0kh z 4 0 .0kh z 8 0 .0kh z fs=4 4. 1 k hz f s =96k h z f s =192 kh z fr fr fr - - - 0. 2 0. 3 1. 0 - - - db db db not e 8. t h e pa ssba n d an d st o pba n d fre que n c i e s scal e wi t h fs. fo r e x am pl e, 2 1 . 8 k h z at ? 0 . 1 db i s 0. 45 4 x f s ( dac ). the r e fere nce fre qu ency o f t h ese r e sp onse s i s 1k hz. no te 9. th e pa ssb an d and stopb a nd frequ e ncies scale with fs (system sa mp lin g rate). for example, pb=0.4535fs ( @ 0. 05 db ) , s b =0. 5 4 6 f s. no te 1 0 . th e calcu l atin g d e lay ti me o ccu rred b y d i g ital filt erin g . th is ti me is fro m an in pu t o f t h e an al o g sig n a l un til 2 4 b i t dat a o f b o t h ch annel s i s set i n t o t h e out put re gi st er of p or t 1. fo r d ac , t h i s t i m e i s from set t i ng 16/ 24 bi t dat a of b o t h ch ann e ls i n to t h e inpu t regi ster o f port2 u n til an an al o g signal is o u t p u t .
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 9 - dc cha ra cteristics (ta= 25 c; av dd1 =avd d2 = d vdd = 3 . 3 v ) parameter symbol min typ max unit hi g h -le v el in put v o l t a ge low-lev e l inpu t vo ltag e vi h vil 7 0%dvd d - - - - 3 0%dvd d v v hi g h -le v el ou t put vol t a ge (i out = -4 0 0 a) lo w-le vel ou t put vol t a ge (i out = - 4 0 0 a (exce pt s d a p i n), 3m a(s da pi n )) vo h vo l d vdd -0 .4 - - - 0. 4 v v input leakage current iin - - 10 a switching chara ct eristics (ta=2 5 c; avd d1 =a vdd 2 =dv dd = 3 . 3v ; c l = 20p f (ex cep t fo r sda p in) , c b =400 pf(sda p in) ) par a meter sym bol min typ max unit master cloc k timing fre que ncy duty feclk dec l k 8. 192 40 50 3 6 .864 60 mh z % master cloc k 2 56f sn, 1 28f sd: pul s e wi dt h l o w pul s e wi dt h h i gh 3 84f sn, 1 92f sd: pul s e wi dt h l o w pul s e wi dt h h i gh 5 12f sn, 2 56f sd, 128 f s q : pul s e wi dt h l o w pul s e wi dt h h i gh 7 68f sn, 3 84f sd, 192 f s q : pul s e wi dt h l o w pul s e wi dt h h i gh fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh 8. 192 0. 37 0. 37 1 2 .288 0. 37 0. 37 1 6 .384 0. 37 0. 37 2 4 .576 0. 37 0. 37 1 2 .288 1 8 .432 2 4 .576 3 6 .864 mh z 1/ fc l k 1/ fc l k mh z 1/ fc l k 1/ fc l k mh z 1/ fc l k 1/ fc l k mh z 1/ fc l k 1/ fc l k lrck1 timing (slav e mo de) duty cy cle fsn duty 32 45 48 55 khz % lrck2 timing (slav e mo de) normal speed mode d oub le sp eed mod e qua d spee d m ode duty cy cle fsn fsd fsq duty 32 32 128 45 48 96 192 55 khz khz khz % lrck1 timing (mas ter mode ) norm al speed mode duty cy cle fsn duty 32 50 48 khz % power-down & rese t timi ng pd n p u lse wi dth ( not e 1 1 ) pdn ? ? to sdto v a lid ( note 1 2 ) tpd tpdv 150 2 640 ns 1/ fs no te 11 . refer to th e ? sy st em r e set ? para gra p h f o r t h e r e set by p d n1 and p d n 2 pi n s . not e 1 2 . a ft e r a ri si n g e dge o f p d n1 , t h e i n t e rnal c o unt er s t art s by di vi de d cl oc k o f m c lk a n d adc p o we r d o w n i s rel eased by a f a l l i ng ed ge o f c v ee a f t e r 6 4 / fs o n lr c k , t h en s d ti o i s out put 5 28/ fs l a t e r.
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 10 - par a meter sym bol min typ max unit audi o i nter f ace timing (sl ave mode ) por t 2 ( da c) bick2 period bick2 pu lse w i d th lo w pul s e wi dt h h i gh lrck2 edg e t o bic k 2 ? ? ( note 1 3 ) bick2 ? ? to lrck2 edg e ( note 1 3 ) sdt i hol d ti m e sdt i set u p ti m e tbck tbckl tbckh tlrb tblr tsdh tsds 81 20 20 20 20 10 10 ns ns ns ns ns ns ns por t 1 ( adc) bick1 period bick1 pu lse w i d th lo w pul s e wi dt h h i gh lrck1 edg e t o bic k 1 ? ? ( note 1 3 ) bick1 ? ? to lrck1 edg e ( note 1 3 ) lrck1 to sdto (msb) bick1 ? ? to s d to tbck tbckl tbckh tlrb tblr tlrs tbsd 324 128 128 80 80 80 80 ns ns ns ns ns ns ns audi o i nterface timing (master mode) bic k 1 f r eq ue ncy bick1 du ty bick1 ? ? to lrck1 edg e bick1 ? ? to s d to fbck d bck tmblr tbsd -2 0 64 fs 50 20 20 hz % ns ns contr o l interface timing (i 2 c bus ): sc l c l oc k f re que ncy bus f r ee tim e between tra n sm issions start con d ition ho ld tim e (p rio r to first cl ock p u lse) c l ock l o w ti m e c l ock hi g h ti m e setu p tim e fo r rep eated start con d ition sda hol d ti m e from scl falling ( note 1 4 ) sda set u p ti m e from scl rising rise tim e of b o th sda a n d s c l lines fall tim e of b o th sda a n d s c l lines setu p tim e fo r stop c o nd ition pu lse wid t h o f sp i k e no ise su ppressed b y in pu t filter cap acitiv e lo ad o n bu s fscl tbuf thd:st a tlow thi gh tsu:st a thd:d a t tsu:dat tr tf tsu:st o tsp cb - 1. 3 0. 6 1. 3 0. 6 0. 6 0 0. 1 - - 0. 6 - 0 400 - - - - - - - 0. 3 0. 3 - 50 400 khz s s s s s s s s s s ns pf not e 1 3 . b i c k ri si n g e dge m u st not occ u r at t h e sam e t i m e as lr c k e d ge. no te 14 . data must be held for sufficient time to bridge the 300 ns transition time of scl. note 15. i 2 c-bus is a trademark of nxp b.v.
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 11 - timing diagram 1/f c lk tclkl vih tclkh mc l k vil 1/f s n, 1/f s d, 1 / f s q lrck vih vil tbck tbc k l vih tbckh bic k vil c l ock ti m i ng (n orm a l m ode) tlrb lrck vi h bick vil tl rs sdto 50% tvdd tbsd vih vil tb lr ts ds sdti vih vil tsdh au di o i n t e r f ac e ti m i ng lrck= lrc k 1, lrc k 2 bick= b i ck1, bic k 2
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 12 - lr c k bick sdto tbsd tmblr 50% d v d d 50% d v d d 50% dvdd au di o i n t e r f ac e t i m i ng (m ast e r m o de ) tp d vi l p dn tp d v sdto 50% dvdd vi h po wer d o wn & reset tim i n g thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat ts u:s t a stop start start stop tsu:sto vi l vi h vi l ts p i 2 c b u s m ode tim i ng
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 13 - operation overvie w s y s t em c l ock the AK4688 has two a udi o se rial interfaces (port 1 a n d port2) which can be ope rate d asy n chronously. the port 2 i s th e audi o d a ta i n terface fo r dac, and th e port1 is for adc. at each port, t h e ex t e r n al cloc ks, w h i c h a r e re q u i r e d t o ope rate the a k 4 6 8 8 in slave m ode, are m c lk 1 (m cl k 2 ) , lrck 1 (lr c k2 ) a n d bic k 1 (b ick 2 ) . t h e m c l k 1 (mckk2) m u st b e sy n chron ized with lrc k 1 (lrck2 ) bu t th e p h a se is no t critical. the a k 4 6 8 8 h a s i n depe n d ent p o we r- d o w n f unct i o n f o r a d c an d dac c o nt r o l l e d by t h e pd n1 an d pd n2 pi ns (o r pw a d and pw da b its ) . in i 2 c co ntr o l m ode, t h e ak 4 6 8 8 i s i n no rm al ope rat i o n whe n p d n1 pin= p dn 2 pin= ?h? an d pwad b it = pwda b it = ?1? ( table 1 , table 3 ) . i n h/ w c ont rol m ode ( table 2 , table 4 ) , t h e a k 46 88 is in n o r m al ope rat i o n whe n p d n1 pi n = pd n2 pi n = ?h ?. the a k 4 6 8 8 i s a u t o m a t i c al l y powe r e d d o w n w h en m c lk 1 cl oc k i s st op pe d i n m a st er m ode (m s n pi n = ?h? ), or w h e n m c l k1 (m c l k2 ), lr c k1 (lr c k2 ) a n d b ic k 1 (b ic k 2 ) are st op pe d i n sl a v e m ode (m sn pi n = ?l? ) . i n t h i s case , t h e a d c out p u t i s ? 0 ? dat a a n d d a c out p u t i s p u l l e d d o w n t o vss . th e po w e r - dow n state is r e leased and th e ak 468 8 star ts op er ation wh en mclk 1 is inpu t in m a ster mo d e ( m sn p in = ?h?), o r wh en mclk1 (mclk2), lrck1 (lrck2) an d b i ck1 (bick2) are i n put in slave m ode (msn pin = ?l?). whe n the reset is released (p dn 1/2 pin = ? l ? ? h ?), such as a f ter power up the d e v i ce, th e adc/dac of ak46 88 is in p o wer-d o wn st ate u n til mclk1 / 2 , lrck1 / 2 an d bic k 1 / 2 are i n pu t. pd n1 pi n p wad bi t m a st er m ode: m c lk1 sl ave m ode: m c lk1 ,lr c k 1 an d b i c k 1 adc stauts adc o u t l power down 0 h 0 po wer d o w n 0 h 1 n on- activ e pow e r down 0 h 1 active po wer u p adc output (: d o n?t care ) table 1. sy stem clock fo r adc ( i 2 c contro l mod e , port1 ) pd n1 pi n m a st er m ode: m c lk1 slave m ode: m c lk1,lrck1 and bic k 1 adc stauts adc o u t l po wer d o w n 0 h n on- activ e pow e r down 0 h active po wer u p adc output (: d o n?t care ) tabl e 2. sy st em c l oc k fo r adc ( h / w c o nt r o l m o de, p o r t 1 ) pd n2 pi n p wda bi t mclk 2,lrck 2 and bic k 2 dac stauts dac o u t l power down vss h 0 po wer d o w n vss h 1 n on- activ e pow e r down vss h 1 active po wer u p dac o utput (: d o n?t care ) table 3. sy stem clock fo r dac ( i 2 c contro l mod e , port2 ) pd n2 pi n mclk 2,lrck 2 and bic k 2 dac stauts dac o u t l power down vss h n on- activ e pow e r down vss h active po wer u p dac output (: d o n?t care ) tabl e 4. sy st em c lock for dac (h/w control mode, port2)
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 14 - master/slave mode the m s n pi n c ont rol s m a st er/sl a ve m ode of t h e p o r t 1. t h e p o r t 2 s u p p o rt s sl ave m ode o n l y . i n m a ster m ode, lr c k 1 and b i c k 1 pi n s are o u t p ut pi ns. i n sl a v e m ode, lr c k 1 ( l r c k 2 ) a n d b i c k 1 (b ic k 2 ) pi ns are i n p u t pi ns ( table 5 ). m s n pi n port 1 (adc) bick1 , lrc k 1 port 2 (dac) bick2 , lrc k 2 l input (slave mode) input (slave mode) h output ?l?(master mode) input (slave mode) tabl e 5. m a st e r / sal ve m ode port1 (a dc) clock c ontrol in m a st er m ode (m s n pi n = ?h?) , t h e re qui red cl oc k i s m c lk 1. th e c k s1 -0 b its and th e c k s pin s elect the clock fre que ncy ( table 6 , table 7 ). th e adc is in p o wer-d o wn st ate u n til mclk1, bic k 1 and lrc k 1 are su pp lied . c ks 1 bi t c ks 0 bi t c l ock spee d 0 0 25 6 fs 0 1 38 4 fs 1 0 51 2 fs 1 1 76 8 fs (de faul t ) tabl e 6. por t 1( a d c ) m a st e r c l oc k c ont r o l (m ast e r m o d e , i 2 c c ont rol m ode ) c ks pi n c l ock spee d l 256fs h 768fs tabl e 7. por t 1( a dc ) m a st e r c l oc k c ont r o l (m ast e r m o d e , h/ w c ont r o l m ode ) in sl ave m ode (m sn pi n = ? l ?), re qui re d c l ocks are m c l k 1 , b i c k 1 a n d lr c k 1 . t h e m a st er cl ock ( m c l k1 ) m u st be syn c hron ized with lrc k 1 bu t th e ph ase is n o t critical. aft e r e x i t i ng reset f o l l o wi ng a po wer - u p (p d n 1 pi n = ?l? ?h?), th e adc of ak46 88 is in power-down state un til mclk1 , lrc k 1 an d bic k 1 are in pu t. th e ad c on ly supp or ts n o rmal sp eed m o d e ( f s = 3 2 k ~ 4 8kh z). lrck1 mclk1 (m hz) bick1 (m hz) fs 2 56f s 3 84f s 5 12f s 7 68f s 64fs 32 .0 k hz 8. 19 2 0 12 .2 8 80 16 .3 8 40 24 .5 7 60 2.0480 44 .1 k hz 11 .2 8 96 16 .9 3 44 22 .5 7 92 33 .8 6 88 2.8224 48 .0 k hz 12 .2 8 80 18 .4 3 20 24 .5 7 60 36 .8 6 40 3.0720 tabl e 8. por t 1( a d c ) sy st em cl ock e x am pl e
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 15 - port2 (d ac) clock c ontrol ex tern al clo c ks (mclk2, bick2 and lrc k 2) m u st always b e p r esen t wh en ev er th e dac is in no rmal o p e ration (pdn pin = ?h? or pwda2 bit= ?1?). t h e m a ster clock (mclk2) m u st b e sy n c h r on ized with lrck2 bu t the ph ase is no t critical. mclk2 cloc k is use d for interp olation filter and delta sigm a m odulator. duri ng ope ration, dac is a u tom atically reset and t h e a n al o g out put g o es t o 0v (ty p ) i f m c lk 2, l r c k 2 a n d bi c k 2 are st o p p e d. thi s reset i s rel ease d , a n d t h e dac starts o p eratio n wh en mclk2, lrc k 2 and b i ck2 ar e i n pu t ag ain . th e dac is in power-down m o d e un til mclk 2, bi c k 2 and lrck2 ar e su pp lied . th ere are t w o m o d e s fo r co n t ro lling t h e sam p lin g sp eed o f dac . one is the manu al settin g m o d e (ac k s b it = ?0 ?) usin g th e dfs1 -0 b its, an d th e o th e r is au to setting m o d e (acks b it = ?1 ?). 1 . manua l sett ing mo de (ac k s bit = ? 0?) wh en th e ac ks b it = ?0 ?, dac is in manu al setting m o d e and th e sam p lin g sp eed is selected b y dfs1 -0 b its ( table 9 ). dfs1 bit dfs0 bit dac sam p lin g sp eed (fs) 0 0 no rm al speed mode 32khz~48khz 0 1 d oub le speed mode 64khz~96khz (default) 1 0 qua d spee d m ode 12 8 k hz~ 1 92 k h z 1 1 not a v ai lable - tab l e 9 . port2(dac) sam p l i n g sp eed (acks b it = ?0 ?, man u a l settin g mod e ) lrck2 mclk2 (m hz) bick2 (m hz) fs 2 56f s 3 84f s 512fs 768fs 64fs 32 .0 k hz 8. 1 920 12.2880 16.3840 24.5760 2.0480 44 .1 k hz 11 .2 8 96 16.9344 22.5792 33.8688 2.8224 48 .0 k hz 12 .2 8 80 18.4320 24.5760 36.8640 3.0720 tab l e 1 0 . por t 2 ( dac) system c l o c k ex amp l e (no r m a l sp eed mod e @man u a l settin g mod e ) lrck2 mclk2 (m hz) bick2 (m hz) fs 1 28f s 1 92f s 256fs 384fs 64fs 88 .2 k hz 11 .2 896 16.9344 22.5792 33.8688 5.6448 96 .0 k hz 12 .2 880 18.4320 24.5760 36.8640 6.1440 tabl e 11 . p o r t 2( d a c ) sy st e m cl ock e x am pl e( do u b l e s p eed m ode @m anual set t i ng m ode ) lrck2 mclk2 (m hz) bick2 (m hz) fs 1 28f s 1 92f s 256fs 384fs 64fs 17 6. 4 khz 22 .5 7 92 33.8688 - - 11.2896 19 2. 0 khz 24 .5 7 60 36.8640 - - 12.2880 tabl e 12 . p o r t 2( d a c ) sy st em cl ock e x am pl e ( q uad s p e e d m ode @m a nual set t i ng m ode )
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 16 - 2. au to se ttin g mode (ack s bit = ?1?) wh en t h e ac ks b it = ?1 ?, dac is in au to setting m o d e and th e sam p li n g sp eed is sel ected au t o m a t i cally b y th e rat i o of mclk 2 / lrc k 2, as show n in tabl e 13 and table 14 . i n this m o d e , th e settin g s o f d f s1- 0 b its ar e ignor ed. m c lk2 dac sam p l i ng s p ee d (fs ) l r c k2 512fs, 768fs normal speed mode 32khz~48khz 256fs, 384fs double speed mode 64khz~96khz 128fs, 192fs quad speed mode 128khz~192khz tabl e 13 . p o r t 2( d a c ) sam p l i n g s p eed ( a c k s bi t = ? 1 ?, a u t o set t i ng m ode ) lrck mclk (m hz) f s 1 28f s 1 92f s 2 56f s 3 84f s 5 12f s 7 68f s 1 152 f s sampling speed 32.0khz - - - - 16.3840 24.5760 36.8640 44.1khz - - - - 22.5792 33.8688 - 48 .0 k hz - - - - 24 .5 7 60 36 .8 6 40 - normal 32 .0 k hz 8. 19 2 12 .2 8 8 44 .1 k hz 11 .2 8 96 16 .9 3 44 4 8 .0kh z 1 2 .288 1 8 .432 88.2khz - - 22.5792 33.8688 - - - 96 .0 k hz - - 24 .5 7 60 36 .8 6 40 - - - double 176.4khz 22.5792 33.8688 - - - - - 192.0khz 24.5760 36.8640 - - - - - qua d tabl e 14 . sy st em c l ock e x a m pl e w h en mclk= 2 56f s/38 4f s, th e ak4 688 sup p o r ts sam p lin g r a te o f 32 kh z~ 9 6kh z ( table 15 ) . ho weve r, w h en t h e sam p lin g rate is 32k hz~ 4 8khz, dr and s/n will d egr ad e as co m p ared to wh en mclk= 5 12fs/76 8fs. m c lk dr, s/n 256fs/384fs 102db 512fs/768fs 105db tabl e 15 . m c lk fre que ncy and dr , s/ n ( f s = 48 k h z) de-emph asis filter th e dac of ak468 8 in cl u d e s a d i g ital d e -em p h a sis filter (tc=5 0 / 15 s) b y iir filter. settin g th e dem1 bit to ?1 ? en ab les the de -em phasis filter. re fer t o ?filter char acteristics ? about the gai n e r ror whe n t h is filter is on. the d e-em p h asis filter is off i n do ub le sp eed mo d e (mclk2 = 25 6fs/38fs ) an d qu ad sp eed m o d e (mclk2 =128 fs/ 1 92fs). th e filter settin g is ex ecu ted in i 2 c con t ro l m o d e an d dem b it con t ro ls on/ off of t h e filter. ( table 16 ) dem b it de-em p h asis filter 1 on 0 off (d efau lt) tabl e 16 . de-e m phasi s c ont r o l ( n orm a l speed m ode )
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 17 - digital high pass filt er th e a d c h as a d i g ital h i gh pass filter fo r dc o f fset can cel latio n . th e cu t-o f f frequ e n cy of th e h pf is 1 . 0 h z at fs=48kh z and freque ncy response scales with sam p ling rate (fs ) . audio serial interface format each por t 1/ 2 can sel ect a u d i o i n t e r f ace f o r m at i ndepe n d e n t l y . the di f1 bi t c o nt rol s au di o dat a f o rm at of t h e p o r t 1. the di f2 1 - 2 0 bi t s co nt r o l t h e au di o dat a fo r m at of t h e p o r t 2. in all m o d e s t h e serial data is msb-first, 2?s co m p le men t fo rm at . the s d t o pi n i s cl ocke d o u t on t h e fal l i ng e d ge o f b i c k 1 a n d t h e sdt i pi n i s l a t c hed o n t h e ri si ng e dge of b i c k 2. sdt i i n p u t fo rm at s can be use d f o r 16 - 2 4 b i t dat a b y zeroi ng t h e u n u s ed lsb s . 1. port 1 ( adc) set t i ng the msn pin and dif1 bit s elect fo llow ing fo ur ser ial d a t a fo r m ats ( table 17 ). lrck1 bick1 m ode m s n pi n di f1 b it sdt o l/r i/o spee d i/o 0 l 0 24/16 bi t left ju stified h/l i 48 fs or 32 fs i (de f ault) 1 l 1 24bit, i 2 s l/h i 48fs i 2 h 0 24bi t left ju stified h/l o 64 fs o (de f ault) 3 h 1 24bit, i 2 s l/h o 64fs o table 17. audi o inte rface format (adc ) 2. por t 2 ( dac) sett i ng th e dif21-20 b its select fo llowing fou r serial d ata fo rm ats ( tabl e 18 ). lrck2 bick2 m ode di f2 1 b it di f2 0 b it sdt i l/r i/o spee d i/o 0 0 0 16bit, right justified h/l i 32fs i 1 0 1 24bit, right justified h/l i 48fs i 2 1 0 24bit, left justified h/l i 48fs i (default) 3 1 1 24bit, i 2 s l/h i 48fs i table 18. audio inte rface format (dac)
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 18 - lr c k bi c k( 6 4 f s ) s d t o (o ) 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 23 1 22 0 23 22 12 11 10 0 23 sd t i ( i ) 1 14 0 15 8 7 1 14 0 15 8 7 lch data rch data do n ? t ca r e do n ? t ca r e 1 2 1 1 10 sd t o - 2 3 : m s b, 0 : l s b; s d t i - 1 5 : m s b, 0 : l s b fi gu re 4. p or t 1= m ode 0/ 2 , por t 2=m o de 0 ti m i ng lr c k bi c k ( 6 4 f s ) sd t o ( o ) 0 1 2 8 9 10 24 25 31 0 1 2 8 9 10 24 25 31 0 23 1 22 0 23 22 16 15 14 0 23 sd t i ( i ) 1 22 0 23 8 7 1 22 0 23 8 7 2 3 : m sb, 0 : l sb lch data rch data don?t car e don?t ca r e 16 1 5 14 fi gu re 5. p or t 1= m ode 0/ 2 , por t 2=m o de 1 ti m i ng lr c k bi c k ( 6 4 f s ) sd t o ( o ) 0 1 2 2 1 2 2 23 24 3 1 0 1 2 0 23 1 22 1 23 22 23 sd t i ( i ) 22 23 0 22 23 2 3 : m sb, 0 : l sb lch data rch data don?t car e 2 2 1 28 29 30 23 0 22 2 3 24 31 1 0 don?t care 2 21 28 2 9 30 0 fi gu re 6. p or t 1= m ode 0/ 2 , por t 2=m o de 2 ti m i ng lr c k bi c k ( 6 4 f s ) sd t o ( o ) 0 1 2 3 2 2 23 24 2 5 0 0 1 sd t i( i ) 31 29 30 23 22 1 22 23 0 2 3 : m sb , 0 : l sb lch data rch data don?t car e 2 2 1 0 2 3 22 23 24 25 0 31 29 30 23 22 1 22 23 0 don?t care 2 21 0 1 fi gu re 7. p or t 1= m ode 1/ 3 , por t 2=m o de 3 ti m i ng
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 19 - pre-amp and input a tt th e i n pu t attenu atio n circu it is con s tru c ted by co nn ecting i n pu t resi st or s ( r i ) t o l i n/ r i n pi n a n d feed back resi st ors ( r f) bet wee n l i/ r i pi n a n d l o/ r o pi n ( figure 8 ). th e inpu t vo ltag e to leran c e of th e lo/r o p i n is typ i cally 1 . 91vrm s. there f ore, e x c e ssi ve i n p u t s s u ch as 2v rm s or 4v rm s t o t h e li n/ r i n pi n vi a r i resi st o r s m u st be at t e n u a t e d t o 1. 9 1 v r m s by t h ese r i an d r f resi st ors . tabl e 19 shows resistance exa m ples of ri a n d rf. lin li lo pre-amp ri r f fi gu re 8. pre - am p and i n put att i npu t rang e ri ( k ? ) rf ( k ? ) att gain ( d b ) lo/ro pin adc o u tp ut (t y p ) 4v rm s 47 20 -7 .4 2 1. 70 v rm s -1.0dbfs 2. 2v rm s 47 39 -1 .6 2 1. 82 v rm s -0.39dbfs 1v rm s 47 82 +4. 83 1. 74 v rm s -0.78dbfs tabl e 19 . i n put att exam pl e
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 20 - charge pump circuit the i n t e rnal c h arge p u m p ci rcui t ge nerat e s n e gat i v e vol t a ge (c v ee) f r om c v d d v o l t a ge f o r a n al o g i n p u t an d o u t p ut . the po we r up t i m e of cha r ge pum p ci rcui t i s 1. 3m s@48 k h z. whe n p wa d a n d p wd a bit s = ?1? , t h e adc a n d dac are p ow e r e d- up af t e r th e ch ar g e pu m p cir c u it is p ow e r e d- up . th e po wer-up co nd itio ns o f t h e ch arg e pu mp circu it are: i 2 c c o nt r o l m ode ? pd n1 pi n = ? h ?, p w a d bi t = ?1? an d m c lk 1, lr c k 1 an d bi c k 1 ( m clk 1 on ly in master m o d e ) ar e inpu t. ? pd n2 pi n = ? h ?, p w d a bi t = ?1? and mc lk2 , lrc k 2 an d bi c k 2 ar e in pu t. h/ w c o nt rol m ode ? pd n1 pi n = ?h ? a n d m c lk 1, lr c k 1 a n d b i c k 1 (m c k 1 onl y i n m a st er m ode) a r e i n p u t . ? pd n2 pi n = ? h ? a n d m c lk 2, lr c k 2 a n d b i c k 2 are i n p u t . pdn1 pi n pw a d b it m a st er m ode: m c lk1 slave m ode: mclk1,lrck1, bic k 1 pdn2 pi n pw d a b it mclk 2, bi c k 2, lrc k 2 cp statu s h 1 active on x x h 1 active on (: d o n?t care ) tab l e 2 0 . ch arg e pu m p power on con d ition s (i 2 c c ont rol m o de) pdn1 pi n ma st er m ode: m c lk1 sl ave m ode: m c lk1 , lr c k 1, b i c k 1 pdn2 pi n mclk 2, bi c k 2, lrc k 2 cp statu s h active on x h active on (: d o n?t care ) tab l e 2 1. charge pump power on conditions (h/w control mode) dv dd cha r g e pu m p cp c n dvs s vee 1u f 1u f neg at i v e powe r a k4688 (+ ) cb ca (+ ) fi gu re 9. c h a r ge p u m p c i rcu i t note: c o nnect a 1f low e s r capacitor bet w een cp a n d c n pi ns, an d b e t w een d v ss and v ee pi ns .
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 21 - analog in put/output (lin /rin, lo ut/rout pins) power sup p l y v o ltag e fo r analo g inpu t/o u t p u t is app lied fr o m a reg u l ato r for po sitiv e p o wer and a ch arg e-pum p fo r n e g a tiv e p ow e r. th e an alog ou tpu t is sing le-en d e d and cen t e r e d on 0v (av s s2) . th er efo r e, a cap acitor fo r a c - c oup lin g can be rem oved. the m i nim u m load resistance is 5k . wh en t he d ac i n put si g nal l e vel i s 0 db f s , t he out put v ol t a ge is 2v rm s. soft mute the d a c ha s a soft m u t e func t i on. t h e so ft m u t e operat i o n i s perf orm e d at di gi t a l dom ain. whe n t h e s m ute bi t g o e s t o ?1 ?, th e i n pu t data is atten u a ted b y - i n 1 024lrck cycle. w h en th e sm u te b it r e tu rns to ?0 ?, th e m u te is can celled an d th e atten u a tion lev e l g r adu a lly ch ang e s t o 0db in 10 24 lrc k cycle. if t h e so ft m u te is can celled b e fo re atten u a tin g t o - after starting t h e op eration , t h e atten u a tion is d i scon tinu e d an d th e attenu atio n lev e l ret u rns to 0 d b i n th e sam e c y cle. t h e so ft m u te is effectiv e fo r ch ang i ng th e sign al sou r ce witho u t stop p i n g th e si g n a l t r an sm issi o n . smu t e b i t atte nuation level 1024/f s 0db - lo ut/rout 1 024/fs gd gd (1) (2 ) (3 ) notes: (1) in no rm al sp eed m o d e , t h e inpu t d a ta i s atten u a ted to - ? in 1024l rck cycle. t h is tim e is 2048lrck cycles (2 0 48/ f s ) i n d o u b l e s p ee d m ode , a n d 4 0 9 6 l r c k cycl e ( 4 09 6/ fs ) i n qua d s p ee d m ode . (2 ) t h e a n alo g out put c o rresp on din g t o t h e d i git a l i nput has g ro u p del a y , gd . (3) if t h e soft m u te is can celled b e fore attenu atin g t o - aft e r startin g t h e o p e ration , th e atten u a tio n is disco n tinu e d and th e atten u a tion lev e l ret u rn s t o 0 d b in t h e same cycle. fi gu re 1 0 . so ft m u t e f u nct i o n s y s t em r eset whe n po we r- u p t h e ak 4 6 8 8 , t h e pd n 1 an d p d n 2 pi ns s h o u l d be ?l? and c h a nge d t o ?h? a f t e r al l po we r su p p l i e s ( dvd d, av dd 1, and av dd 2) ar e su pp lied . af ter th is res et is release d (pdn1 a n d pdn2 pins = ?l? : ?h ?), all b locks are in power-do w n m o d e . this en su res th at all in tern al reg i st ers are reset to th eir in itial v a lu es. adc in tern al circu i t, cont rol regi st e r s f o r a d c ( a dd r: 0 1 h - 0 2h ) and p w a d bi t are reset by p d n 1 pi n = ? l ?. d a c i n t e r n al ci rcui t , co nt rol regi st ers f o r d a c ( a dd r: 03 h ) a n d p w d a bi t are re set by t h e pdn2 pin = ? l?. whe n both pdn1 and pdn2 pi ns a r e ?l ?, all b lo c k s , reg i sters an d ch arg e pu m p are po wered - d o wn . in h/ w con t rol m o d e , reg i ster setting s are i g nored, an d th e po we r- do w n c ont rol by p d n 1 a n d p dn 2 pi ns a re a v ail a ble.
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 22 - po w e r o n /off sequ ence the adc and dac bl ocks of the AK4688 a r e placed i n powe r-down m ode by bri ngi ng the pdn1 pi n a n d pdn2 pin to ?l? resp ectiv el y and bo th d i g ital filters are reset at th e sam e ti m e . th e pdn1 p in = pdn2 p in =?l? also reset th e con tro l regi st ers t o t h ei r defa ul t val u es . i n p o we r- d o w n m ode, t h e d a c out put s 0 v an d t h e s d t o pi n g o es t o ?l? . t h i s re set m u st always be exec uted a f ter power-up. in m a ster m ode, the adc starts operatio n o n t h e ri si n g e d ge of m lc k 1 aft e r po wer - d o w n m ode i s rel eased by a st at us change of the pdn1 pi n from ?l? to ?h?. in sl ave m ode, w h en po wer d o w n m ode i s released by a st atus c h ange of the pdn1 pi n from ?l? to ?h?, the adc st art s o p erat i o n on t h e ri si n g e d g e of lr c k 1 f o l l o wi ng m l c k 1 , lr c k 1 and bick1 inpu ts. the dac start s operation on the risi ng of t h e lr c k 2 , aft e r po we r- do w n m ode i s rel ease d by a st at us c h a nge o f t h e p d n2 pi n fr om ?l? t o ? h ?, a n d m c lk 2, lr c k 2 and b i c k 2 are i n p u t . th e an alog in i tializa tio n cycle of adc starts after ex iti n g t h e p o w er -d o w n m ode. the r ef ore , t h e out put dat a , s d t o b eco m es av ailab l e after 26 40 cycles o f lrck1 clo c k . in case o f t h e dac, an an al o g i n itializatio n cycle starts after ex iting th e p o wer-d o wn m o d e . th e an alog ou tpu ts are 0v du ring th e i n itializat io n . figure 11 sho ws po w e r -dow n an d p ow e r -u p sequence . th e adc and dac can b e po wered - d o wn i n d i v i du ally b y pwad and pwda b its. reg i ster v a lu es are no t in itialize d b y these bits. whe n pwad bit = ?0?, t h e adc out put g o es t o ?l?. whe n p wda bi t = ? 0 ?, the dac output goes t o 0v. a dc interna l sta te cl ock in mc lk 1 , l r ck 1,b i ck 1 mc lk 2 , l r ck 2,b i ck 2 a dc in ( a nal og) a dc out (digital) dac internal sta te dac in (di g it al) dac out (i nter nal statu s ) p o w e r-d o w n do n?t c a re gd ?0?data power- do wn ?0?data gd (5) (5 ) (6 ) ti m e a init cycle normal operation (3) gd no rm al opera t io n gd (4) ?0 ? d at a ?0?d at a don? t c a re (2) pdn1 pi n = pdn2 pi n powe r (1) (7) 0v cve e 0v cvee pin ti m e b (9) (8) 0v 80% av d d 2 vref1 /2 pi n figure 1 1 . po w e r- up/ do w n se que nce e x am pl e
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 23 - notes: ( 1) th e pdn1 an d pd n2 p ins shou ld b e c h a nge d from ?l? to ?h? after power up. ?l? ti m e o f 150 ns o r m o re is n eed ed to reset th e ak46 88 . th e pdn p i n s m u st b e h e ld to ?l? un til all power su pp ly pins are fe d. after all powers are rise n up, t h e pdn1 an d pd n2 p ins sh ould b e set to ?h?. (2 ) c h ar ge p u m p circuit po wer - u p : whe n m c l k 1 / 2, b i c k 1/ 2 a n d lr c k 1/ 2 ar e i n p u t a f t e r t h e pd n 1 / 2 pi n = ?l? ?h?, th e vo ltag e on th e cvee p i n r i ses t o cvee vo ltag e appr ox im ate l y in 1.3 m sec@4 8khz. no te: if th e pwad an d pwda b its are set to ?1 ?, o r pd n1 a n d p d n 2 pi ns a r e set t o ?h? d u r i n g a p o we r- u p sequ en ce of the ch arg e -pu m p , adc an d dac are in itializ e d after th e ch arg e -pu m p circu it is p o wered on. (3) th e an alog b l o c k o f adc is in itialized after ex iting th e p o wer-d o wn st ate. ti m e a=5 2 8 / fs (4) th e an alog b l o c k o f dac is initialized after ex iting th e p o wer-d o wn st ate. in case of con n ect i ng a 1f c a paci t o r t o t h e vr ef 2 pi n, t i m eb i s sho w n bel o w. t i m e b = 6/ fs x 8 x 2: n o rm al spee d m ode t i m e b = 12/ fs x 8 x 2: d o ubl e spee d m ode t i m e b = 24/ fs x 8 x 2: qua d s p eed m o de d/a d a ta inpu t b e co m e av aila b l e after th e ti meb p e riod . (5 ) di gi t a l out put s c o r res po n d i n g t o a n al o g i n p u t s an d a n al og o u t p ut s co rr esp o n d i n g t o di gi t a l i nput s ha v e gr o up del a y (g d) . ( 6 ) a d c ou tputs ?0 ? d a ta in po w e r - do wn state. (7 ) c h ar ge p u m p circuit po wer - d o w n (p dn 1 pi n = ? h? ?l? o r n o m c lk 1, b i c k 1 a n d lr c k 1 i n put s ) an d (p dn 2 pi n = ? h ? ?l? or no mclk2, bick2 an d lr ck2 inp u ts) the c v ee pi n o u t p ut bec o m e s 0 v acc or di n g t o a fl y i ng ca p acito r and an in tern al resist or. t h e inte rnal resistance is 50 k ? (t y p ) . there f ore, w h e n t h e c v e e pi n has a fl y i ng c a paci t o r o f 1 f, t h e t i m e con s t a nt i s 5 0 m s ec (t y p ) . (8) it tak e s 20 48 /fs fo r vref1 stab ilizatio n after th e ch arge pu m p is po wered up . (9) it tak es approx im ate l y 5 m sec (typ) u n til vref1 / 2 rise s up after p o wer-down m o d e of adc/dac is released .
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 24 - serial control interface th e ak 468 8 su ppo r ts f a st- m o d e i 2 c-bus sy ste m ( m ax: 400khz ). 1. data t r ansfer in orde r t o acc ess any ic devi ces on t h e i 2 c bus, inp u t a start cond itio n first, fo llowe d by a single slave addres s whic h include s t h e de vice a d dress . ic de vices on the bus c o m p are this slave a d dress with thei r ow n addr esses an d the i c d e v ice w h ich h a s an i d en tical addr ess w ith th e slave- add r ess g e n e r a tes an acknow ledg em en t. th e i c d e v i ce with th e id en tical address exec ut es either a rea d or a write ope ration. after th e co mm an d ex ecu tio n, inpu t a sto p cond itio n . 1- 1. dat a c h an ge ch ang e t h e d a ta on th e sda lin e wh ile scl lin e is ?l?. sda lin e cond ition m u st b e stable and fix e d while th e cloc k is ?h?. ch ang e th e data lin e con d ition b e t w een ?h? an d ?l? o n l y wh en th e clo c k sign al on th e scl lin e is ?l?. ch ang e t h e sda lin e con d itio n wh ile sc l lin e is ?h? on ly wh en th e start cond itio n or stop con d ition is i n pu t. scl sda da t a l i n e st ab l e : dat a valid ch a ng e of da t a a llowed f i g u r e 12 . d a ta t r an s f er 1- 2. st art c o n d i t i on an d st o p c o n d i t i on a start cond itio n is g e n e rated b y t h e tran sitio n o f ?h? to ?l? on th e sda lin e wh ile t h e scl lin e is ?h?. all in stru ctio ns are i n itiated b y a start con d ition . a st o p co nd i tio n is g e n e rate d b y th e transitio n of ?l? to ?h? on sda line wh ile scl li n e is ?h?. all in st ru ction s end by a stop co nd itio n. scl sda st o p c o n d it io n st art co nd it io n fig u r e 13 . sta rt an d stop cond itio n s
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 25 - 1- 3. ac k n o wl e dge an e x ternal de vice that is se nding data t o t h e AK4688 releas es the sda l i ne (? h? ) a f ter receivi ng one -byte of data. an external de vice that receives data from the AK4688 t h en sets the sda line to ?l? at t h e next cloc k. this ope ration is called ?acknowledgem ent?, and it ena b les ve rification that the data tra n sfe r ha s bee n properly e x ec uted. the AK4688 g e n e rates an ack nowledg emen t upo n receip t o f a start con d ition and slav e ad dress. fo r a writ e in stru ctio n, an acknowledgement is ge nerat e d whe n e v er receipt of each byte is com p leted. for a read inst ruction, succee de d by g e n e ration of an ackn owled g e men t, th e ak46 88 releases t h e sd a lin e after ou tpu ttin g data at t h e d e si g n a ted ad dress, and it m o n ito rs t h e sda lin e co nd itio n. wh en th e m a ster sid e g e n e rates an ack nowledg em en t with ou t sen d i n g a sto p co nd itio n, th e ak46 88 o u t p u ts d a ta at th e nex t add r ess l o catio n . wh en no ackno wled g e men t is g e n e rated , th e ak468 8 end s dat a o u t p ut ( n ot ack n o w l edge d) . sc l f r o m m ast er acknowledge dat a ou t p ut b y t r ansmit t e r da t a ou t p u t b y re c e i v e r 1 9 8 start condition c l o c k p u l se f o r a ck n ow l e dg e no t ac k now ledge fig u r e 14 . a c kn ow ledg e on t h e i 2 c-bu s 1-4. fir st b y te th e fi rst byte wh ich in cl u d e s th e slav e-ad dress is inp u t after th e start co nditio n is set, and a targ et ic d e vice th at will b e accessed on the bus is selected by the slav e - address . t h e sl ave-a d dress is configur e d with the upper 7-bits. data of t h e uppe r 6-bits is ?001001?. t h e ne xt 1 bit is the address bit that selects the desi red ic (c ad0 bit). set cad0 bit according to th e c a d0 p i n settin g (c ad0 p i n = ?l?: c a d0 b it = ?0 ?, cad0 p in = ?h?: cad0 b it = ?1 ?). wh en t h e slav e-ad dress is in pu tted , an ex tern al d e v i ce th at h a s th e iden tical device address ge nera tes an ac knowl e dgem e nt and executes commands. the 8 th b it of th e first byte (lsb) is allo cated as r/ w b it. wh en th e r/ w b it is ?1 ?, a read in stru ction is ex ecu ted , and wh en it is ?0 ?, a write in stru ctio n is ex ecu t ed. 0 0 1 0 0 1 c a d 0 r / w figure 15. t h e first byte
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 26 - 2. wr i te ope r at i ons set r/ w b it = ?0 ? for th e w r ite op eration o f th e ak468 8. after recei pt of the start c o ndition and t h e first byte, t h e ak 4688 ge ne rates an acknowle dge , a n d await s the sec o nd by te ( r e g ister ad dr ess) . th e seco nd b y te con s ists o f th e add r ess fo r con tro l r e g ister s of ak 4688 . th e fo r m at i s msb f i r s t, and t hose m o st si gni fi cant 3- b its are ? d on?t ca re?. * * * a4 a3 a2 a1 a0 (* : don?t care) fig u r e 16 . th e second byte after receipt of t h e sec o nd byte, the ak 4688 gene rates a n ac knowledge , a n d a w aits the third byte. t h ose data a f ter the secon d b y te cont ain co n t ro l data. th e fo rm at is msb fi rst, 8b its. d7 d6 d5 d4 d3 d2 d1 d0 fig u re 17 . byte stru ctu r e after th e seco nd b y te th e ak468 8 is cap ab le o f m o re th an o n e byte write opera tion by one sequence . after recei pt of the third byte , the AK4688 gene rates a n ac knowledge, a n d a w aits the ne xt data a g ain. the m a ster can tran sm it m o re th an on e d ata wo rd i n stead of t erm in atin g th e wr ite cycle aft e r th e first d a ta word is t r an sferred . after th e receipt of eac h data, the internal addres s counter is i n crem ented by one , a n d the ne xt data is taken into ne xt address autom a tica lly. if t h e address e x ceeds 03h pri o r t o gene rating a st op c o ndition, the a d dress count er will ?roll over? t o 00h an d th e prev i o u s d a ta will b e o v e rwritten . sd a s t a r t a c k a c k s sl av e a ddress a c k regis t er a ddr es s ( n) da ta (n) p s t o p da ta ( n +x ) a c k data( n +1 ) figu re 1 8 . wr ite o p eratio n
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 27 - 3. r e a d ope r at i ons set r/ w bit = ?1? for a read op e ration of the ak4 688 . the m a st er can rea d next a d dr ess?s dat a by g e nerat i n g a n ac knowledge instead of term inat ing t h e write c y cle after the receipt of the fi rst data word. after the recei pt of eac h data, the i n ternal 3bits ad dress counter is inc r em e n ted by one, a n d th e n e x t d a ta is tak e n in to n e xt ad dress au t o matica lly. if th e ad dres s e x ce eds 0 3 h p r i o r t o gene rati n g st op co n d i t i on, t h e ad dress coun ter will ?ro ll ov er? to 00h an d th e p r ev iou s d a t a will b e ov erwritten . th e ak 468 8 su ppo r ts t w o b a sic r ead op er atio ns: cu rrent add ress rea d and r a n d o m read. 3 - 1 . current address read the AK4688 c ontains a n inte rnal a d dress counte r that m a intains the a d dre ss of t h e last word acces sed, i n crem ented by one . the r efore , if the last acce ss (either a rea d or write) was to address ?n? , the next cur r ent read ope ration woul d access data from the addres s ?n+1? . after recei pt of the slave a d dress with r/ w bit set to ?1? , the AK4688 ge nerates an acknowle dge , tra n s m its 1byte data , wh ich ad dress is set b y th e in t e rn al add r ess co un ter, an d in crem en ts th e in tern al a d dress c o u n t e r by 1. i f t h e m a st er doe s not ge nerat e a n ack no wl ed ge but ge nerat e st op co n d i t i on, t h e ak 4 6 8 8 di s c ont i n ues t r an s m i ssi on sd a s t a r t a c k a c k s slave a ddres s a c k d ata( n) d ata(n+1) p s t o p dat a (n + x ) a c k da t a ( n+2) figure 19. c u rrent address re ad 3 - 2 . ran dom read random read operation allows the m a ster to access an y m e mo ry l o catio n at rando m . prio r to issu ing th e sl av e ad dress with th e r/ w bit set to ?1 ?, the m aster m u st first p e rfo r m a ?d u m m y ? write o p e ration . the m a ster issues a start c o ndition, slave addres s(r/ w bit = ?0?) and t h en the regist er addres s to rea d . after the re gister ad dress?s ackno wled g e , th e master immed i at ely reissu es t h e st art cond itio n and th e slav e ad dress with the r/ w b it set to ?1 ?. th en t h e a k 46 88 g e n e rates an ackn owled g e , 1b yte d a ta an d in crem e n ts th e in tern al ad dres s c o u n t e r by 1 . i f t h e master d o e s n o t g e n e rate an ack nowledg e b u t g e n e rate th e sto p con d ition , t h e ak46 88 d isco n tinu e s transmissio n . sd a s t a r t a c k a c k s s s t a r t sl av e a ddress wo r d a ddr es s(n) slave a ddress a c k da t a ( n ) a c k p s t o p d a t a (n + x ) a c k da t a ( n+1) figu re 2 0 . r a nd om re a d
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 28 - register map ad d r register nam e d7 d6 d5 d4 d3 d2 d1 d0 00 h po wer d ow n/ c ont rol 0 0 0 0 0 0 p wd a p wad 01 h (r eser ved ) 0 0 0 0 0 0 0 0 02 h adc c l ock 0 0 0 di f1 0 c ks 1 c ks 0 0 03 h dac clock 0 ack s dfs 1 dfs 0 dem di f2 1 di f2 0 smute no te: for ad dresses fro m 0 4 h to 1fh, d a ta m u st n o t b e written . all reg i sters are in itialized to th eir d e fau lt v a lu es b y settin g th e pdn1 and pdn2 p i n s t o ?l?. adc i s po we r e d d o wn by se t t i ng t h e p dn 1 pi n t o ?l? . r e gi st ers f o r adc (a d d r: 0 1 h - 02 h) a n d p wa d bi t are in itialized . dac i s po were d d o wn by s e t t i ng t h e p d n2 pin t o ?l? . r e gisters f o r dac (a d d r: 03 h ) an d p w da bit ar e in itialized . adc i s p o we r e d d o w n by se t t i ng t h e p wa d bi t t o ?0? . ho we ver , regi st ers fo r a dc ( ad d r: 01 h- 0 2 h ) a re n o t in itialized . dac is powered d o wn b y set tin g th e pwda b it to ?0 ?. ho wev e r, reg i sters for dac (ad d r: 0 3 h ) is n o t in itialized . the bi t s de fi ne d as 0 m u st cont ai n a ? 0 ? val u e.
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 29 - register definitions ad d r register nam e d7 d6 d5 d4 d3 d2 d1 d0 00h power down/control 0 0 0 0 0 0 pwda pwad r/w rd rd rd rd rd rd r/w r/w default 0 0 0 0 0 0 0 0 p w ad: a d c po wer - d o w n c ont rol 0 : po wer-do wn (d efau lt) 1: n o rm al oper a t i on p w da: d a c po wer - d o w n c ont rol 0 : po wer-do wn (d efau lt) 1: n o rm al oper a t i on ad d r register nam e d7 d6 d5 d4 d3 d2 d1 d0 01h (reserved) 0 0 0 0 0 0 0 0 r/w rd rd rd rd rd rd rd rd default 0 0 0 0 0 0 0 0
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 30 - ad d r register nam e d7 d6 d5 d4 d3 d2 d1 d0 02h adc clock 0 0 0 dif1 0 cks1 cks0 0 r/w rd rd rd r/w rd r/w r/w rd default 0 0 0 0 0 1 1 0 c ks 1 - 0 : p or t 1 (a dc ) c l o c k c ont r o l i n m a st er m o de see table 6 . dif1: port 1 audio f o rm at select see table 17 . ad d r register nam e d7 d6 d5 d4 d3 d2 d1 d0 03h dac clock 0 acks dfs1 dfs0 dem dif21 dif20 smute r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 1 0 0 0 1 0 0 smu te: sof t mu te con tro l fo r da c 0: norm al operation (defa u lt) 1: l out/ r ou t o u t p ut s s o ft - m ut ed di f2 1- 2 0 : p o r t 2 au di o f o rm at sel ect see table 18 . dem : d a c d e -em phasi s re sp onse c o nt r o l see table 16. dfs 1 -0: por t 2 (d ac ) sa m p li ng s p ee d c ont r o l see table 9 . dfs1-0 b its settin g is igno red i n au t o setting mo d e (acks b it = ?1 ?). ack s : p ort 2 (d ac) a uto set t i ng m ode c ont r ol 0: di sa bl e, m a nual set t i ng m ode 1 : en ab le, au t o setting m o de (d efau lt) the mcl k fre que ncy is dete cted aut o m a tic a lly when ac ks b it= ?1 ?. in th is case, dfs1 -0 b its settin g s are igno red . wh en acks b it = ?0 ?, dfs1 -0 bits s e lect the sam p ling spee d m o de, and t h e mclk freq u e n c y is au to m a ti cally d e tected in each m o d e .
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 31 - system de sign figure 21 s h ows t h e system connection diagram . an e v aluatio n bo ar d (a kd4 688 ) d e m o n s tr ates th e o p tim u m layo u t, po we r s u p p l y a rra ngem e nt s an d m easurem ent res u l t s . a k 46 88 en audio dsp1 a n al og i n 1 sdto 2 lrck1 7 mclk2 8 bick2 9 lrck2 36 msn 35 scl 34 sd a 33 i2c 32 lin 31 nc 30 rin 29 li 28 lo 10 sdti 12 test1 13 test2 14 dvdd 15 dvss 16 cp 17 cn 18 cvee 27 ro 26 r1 25 av dd1 24 avs s1 23 avs s2 22 av dd2 21 vr ef 20 lou t 19 ro ut 3 bick1 4 mclk1 5 pdn1 6 pdn2 res e t a nd po w e r do w n audio dsp2 micro controller 47k 47k a n al og o u t 39k 39k 11 cad0 3.3v 1u 0.1u + ( ? ) 1u ( ? ) 3. 3v + 10u 0. 1u + 10u 0.1u 1u ( ? ) 3.3v 3.3v 3. 3v figure 21. ty pical connection diagram (i 2 c c ont rol m o d e , c a d 0 pi n = ?l?, m a st er m ode ) notes: (1 ) use l o w es r (e qui valent series re sistance) ca pacitors for th e capacitors with (*). wh en u s ing po larized cap acito rs, th e p o sitiv e po larity p i n shou ld b e con n ected to th e cp or vref1 /2 p i n , and t h e n e g a tiv e po l a rity p in sh oul d be c o n n ect ed t o t h e c v ee pi n . (2 ) av ss 1, a v ss 2 a n d dv ss m u st be c o nnect e d t o t h e sam e anal og gr ou n d pl ane. (3 ) di gi t a l i n p u t pi ns sh oul d not be al l o we d t o fl oat .
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 32 - a k 46 88 en audio dsp1 a n al og i n 1 sdto 2 lrck1 7 mclk2 8 bick2 9 lrck2 36 msn 35 scl 34 sd a 33 i2c 32 lin 31 nc 30 rin 29 li 28 lo 10 sdti 12 test1 13 test2 14 dvdd 15 dvss 16 cp 17 cn 18 cvee 27 ro 26 r1 25 a v dd1 24 av ss1 23 av ss2 22 a v dd2 21 vr ef 20 lo ut 19 ro ut 3 bick1 4 mclk1 5 pdn1 6 pdn2 res e t a nd po w e r do w n audio dsp2 47k 47k analog out 39k 39k 11 cad0 1u 0.1u + ( ? ) 1u ( ? ) 3. 3v + 10u 0. 1u + 10u 0.1u 1u ( ? ) 3.3v 3.3v 3.3v fi gu re 2 2 . ty p i cal c o n n ect i o n di ag ram (h/ w c ont r o l m ode, m c l k = 7 6 8 fs , m a st er m ode) notes: (1 ) use l o w es r (e qui valent series re sistance) ca pacitors for th e capacitors with (*). wh en u s ing po larized cap acito rs, th e p o sitiv e po larity p i n shou ld b e con n ected to th e cp or vref1 /2 p i n , and t h e n e g a tiv e po l a rity p in sh oul d be c o n n ect ed t o t h e c v ee pi n . (2 ) av ss 1, a v ss 2 a n d dv ss m u st be c o nnect e d t o t h e sam e anal og gr ou n d pl ane. (3 ) di gi t a l i n p u t pi ns sh oul d not be al l o we d t o fl oat .
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 33 - 1. groundin g and po w e r suppl y decoupling the a k 4 6 8 8 r e qui res ca ref u l at t e nt i on t o po wer su p p l y an d g r o u ndi ng ar r a ngem e nt s. a v d d 1 , a v d d 2 a n d d v d d a r e us ual l y su ppl i e d fr om t h e sy st em ?s anal og s u ppl y . i f a v d d 1 , a v d d 2 a n d d v d d a r e su ppl i e d se parat e l y , t h e p o w er u p sequence is not critical. av ss1 , av ss2 a nd dv ss of t h e a k 4 688 must be connec t ed to the s a me analog ground plane. system an alog g r ou nd an d d ig ital gr ou nd shou ld b e w ir e d se paratel y and c o nnecte d toget h er as cl ose a s pos sible to w h er e t h e su pplies ar e bro ught o n t o th e pr in t e d cir c u it bo ard . d e co up ling cap acito r s sh ou ld b e as n ear t o th e ak4 688 as possible, with t h e sm all value cer am ic capacitor being t h e nearest. 2. voltage reference inputs the voltage differe n ce betwee n avdd1 and avss1 sets t h e analog i n put range, and t h e voltage di ffe re nce betwee n av d d 2 an d a v ss 2 set s t h e anal o g out put r a nge . vr ef i s a signal common of t h is ch i p . a 1f ceram ic capacitor connected bet w een the avss1/av s s 2 and vr ef pi ns el i m i n at es t h e eff ect s of hi gh f r e que ncy noi se . no l o a d c u r r en t m a y be d r aw n fr om t h e vr e f pi n. al l si g n a l s , especi al l y cl ocks , s h o u l d be kept a w ay f r om t h e vr e f pi n i n or der t o avoi d un wa nt ed c o u p l i n g i n t o t h e ak 4 6 8 8 . 3. analog in puts the a n al o g i n p u t i s si ngl e - en d e d a n d s u p p l i e d t o t h e p r e-am p vi a e x ternal resistors. select th e fee d back re sistance to m ak e t h e pre -am p ou t put m a t c h t o t h e i n p u t ran g e (t y p . 1. 9 1 v rm s ) of t h e a d c ( l o a n d r o pi n s ). the adc o u t p ut dat a f o rm at is 2 ? s co m p le men t . th e i n ternal d i g ital hpf rem o v e s th e dc o f fset. th e ak46 88 sam p l e s th e an alog i n pu ts at 64 fs. th e d i g ital filter rejects no ise above th e st o p b a nd ex cep t fo r m u l tip les o f 64fs. th e ak 468 8 in clud es an an ti-aliasin g filter (rc filter) t o atten u a te a n o i se aro und 6 4 fs. 4. analog o u tputs the a n al o g o u t put s are si n g l e - e nde d a n d ce nt ered ar ou n d t h e a v ss 2 ( 0 v t y p.) v o l t a ge. t h e out put si g n a l ran g e is typ ically 2 . 0 v rm s (typ @avdd2 =3 .3 v). th e in tern al swi tch ed-cap acitor filter (scf) and con tinu o u s -ti m e filter (ctf) at t e nuat e t h e n o i s e gene rat e d by t h e del t a - s i g m a m odul at o r bey o n d t h e au d i o pass ban d . u s i n g a 1st - o r de r l pf ( figure 23 ) can reduce noise bey o nd t h e audi o pass band. th e ou tpu t vo l t ag e is a po sitive fu ll scale for 7 f ffffh (@ 2 4 b it) and a n e g a tiv e fu ll scal e fo r 80 000 0h (@2 4 b it). th e id eal ou tpu t is 0 v (vss) fo r 00 000 0h (@24b it). th e dc offset is with in 5 m v . l/ r o ut 47 0 2.2nf ak 4 6 88 2. 0v r m s ( t yp ) anal o g ou t ( f c = 154 kh z, g a in = -0 .28 d b @ 40 kh z, g a i n = -1 .0 4d b @ 80 kh z) figu re 2 3 . e x t e rnal circ uit e x am ple1 5. attention to the pcb wiring lin a n d r i n p i ns a re t h e s u m m i ng no des o f t h e p re-am p. att e nti o n s h o u l d be give n t o a voi d c o upl i n g wit h othe r si gn als on t h ose no des . thi s ca n be a ccom p l i shed b y m a ki ng t h e wi re l e n g t h o f t h e i n p u t resi st o r s as s h ort as p o ssi bl e. the sa m e t h eo ry al so ap p l i e s t o t h e li/ r i pi ns an d feed back resi st ors; keep t h e wi re l e ngt h t o a m i ni m u m . unuse d i n p u t pi ns am ong lin an d r i n p i ns m u st be l e ft o p en .
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 34 - package 36-pi n qfn (unit: mm) 6.00 5.70 6.00 5.75 0.85 0.400.10 0.20 0.02 c 0.10 a b m b 0.50 c0. 6 m a x 0.08 c +0.15 -0.05 +0.03 -0.02 +0 . 0 5 -0.07 0. 25 a 4.10 4.10 material & lead finish packa g e m o l d i n g com p o u n d : ep oxy , hal oge n (b r a n d c l ) f r ee lead fram e m a terial: cu lead fram e surface treatm e nt : sol d er (pb fre e) plate
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 35 - marking 4688 xxxx 1 pi n #1 i n di cat i on date cod e : xxxx (4 d i g its) dat e ( y y/ m m / dd ) r e vi si on r eason page c ont e n t s 12/ 05/ 29 00 fi rst e di t i on revision h i story
[ ak4 688 ] ms14 20 -e-0 0 2 012 /05 - 36 - impo rt an t noti ce z these products and thei r s p ecifications a r e s u bject t o c h ange without notice. w h en y o u consid er an y u s e or ap p licatio n of th ese p r od u c ts, p l ease m a k e in qu iries t h e sal e s office o f asah i kasei m i crode vi ces c o r p o r at i o n ( a km ) o r a u t h ori zed di st ri b u t o r s as t o cu rre nt st at us o f t h e pr od uct s . z descri p tio ns of ex tern al circu its, a ppl i cat i o n ci rc ui t s , so f t ware a n d ot h e r related inform at io n co n t ai n e d in th is d o c u m en t are p r ov id ed on ly to illu strate th e o p e ratio n and ap p licatio n ex am p les o f th e semico n d u c tor produ cts. you are fully res ponsible for the i n corp oratio n of th ese ex tern al circu its, app licatio n circu its, software and o t h e r related in fo rm atio n in th e d e si g n o f y o ur eq u i p m en t s . akm assu mes no respo n s i b ility fo r an y l o sses i n curred b y yo u or th ird p arties arising fro m th e u s e o f th ese informatio n h e rein . akm assu m es n o liab ility fo r in fring em en t o f an y p aten t , i n t e l l ect ual pr o p ert y , or ot her ri g h t s i n t h e a p pl i cat i on or us e o f s u ch i n fo r m at i on co nt ai n e d herei n . z any e x p o r t of t h ese p r o d u ct s, or de vi ces o r sy st em s cont ai ni ng th em , m a y r e qu ir e an exp o r t license or othe r official app r oval u n d er t h e l a w a n d re gul at i o ns o f t h e co u n t r y o f e x po rt pe rt ai ni n g t o c u st om s an d t a ri ff s, cu rre ncy e x ch an ge, or st rat e gi c m a t e ri al s. z akm pr o duct s are nei t h er i n t e nde d no r au t h orize d for use as critical co mpone n ts note1 ) in an y safety, life su ppo rt, o r ot he r haza rd r e l a t e d devi ce or sy st em note 2 ) , and akm assu m es n o resp o n sib ility fo r su ch u s e, ex cept fo r th e u s e app r ove d wi t h t h e ex p r ess wri t t e n co nse n t by r e pre s ent a t i v e di rect or o f a k m . as use d h e re: note1 ) a c ri t i cal com ponent i s one wh ose f a i l u re t o f u nct i on or pe rf orm m a y reasona bl y be ex pect ed t o res u l t , wh et h e r d i rectly or i n d i rectly, in th e l o ss of the safety or e ffe ctiveness of the de vice or syste m containing it, a nd wh ich m u st therefo r e m eet ve ry h i gh stand a rd s o f p e rform a n ce and reliab i lity. note2 ) a haza rd rel a t e d devi c e or sy st em i s one de si g n ed o r i n t e nde d fo r l i f e su pp ort or m a i n t e nance o f sa fet y or for applications in m e dicine, aeros pace, nuclear ene r gy, or ot her fields, in wh ich its failure to function or perform m a y reasona bl y be e xpect e d t o resul t i n l o ss of l i f e o r i n si g n i f i cant i n j u ry or dam a ge t o p e rso n o r pr ope r t y . z it is the responsibility of the buyer or distri but or of akm products, who distributes, disp oses of, or otherwise places th e p r od u c t wit h a t h ird p a rty, to n o tify su ch t h ird p a rty in adv a n c e o f th e abo v e co n t en t and con d ition s , an d th e bu yer o r d i stribu tor ag rees to assu me an y and all respo n si b ility a n d liab ility fo r and ho ld akm h a rm less fro m an y an d all cl aim s ari si ng fr om t h e use of sai d pr o duct i n t h e ab sence o f s u ch n o t i f i cat i on.

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